no code implementations • 4 May 2024 • Bing-Yue Wu, Utsav Sharma, Sai Rahul Dhanvi Kankipati, Ajay Yadav, Bintu Kappil George, Sai Ritish Guntupalli, Austin Rovinski, Vidya A. Chhabria
Large language models (LLMs) serve as powerful tools for design, providing capabilities for both task automation and design assistance.
no code implementations • 12 Feb 2024 • Vidya A. Chhabria, Wenjing Jiang, Sachin S. Sapatnekar
Engineering change orders (ECOs) in late stages make minimal design fixes to recover from timing shifts due to excessive IR drops.
no code implementations • 11 May 2023 • Vidya A. Chhabria, Wenjing Jiang, Andrew B. Kahng, Sachin S. Sapatnekar
Inaccurate timing prediction wastes design effort, hurts circuit performance, and may lead to design failure.
no code implementations • 27 Oct 2021 • Vidya A. Chhabria, Vipul Ahuja, Ashwath Prabhu, Nikhil Patil, Palkesh Jain, Sachin S. Sapatnekar
For PDN analysis, we propose two networks: (i) IREDGe: a full-chip static and dynamic IR drop predictor and (ii) EMEDGe: electromigration (EM) hotspot classifier based on input power, power grid distribution, and power pad distribution patterns.
no code implementations • 27 Oct 2021 • Vidya A. Chhabria, Sachin S. Sapatnekar
Power delivery network (PDN) design is a nontrivial, time-intensive, and iterative task.
1 code implementation • 18 Sep 2020 • Vidya A. Chhabria, Vipul Ahuja, Ashwath Prabhu, Nikhil Patil, Palkesh Jain, Sachin S. Sapatnekar
Computationally expensive temperature and power grid analyses are required during the design cycle to guide IC design.