no code implementations • 16 Mar 2018 • Bahar Asgari, Saibal Mukhopadhyay, Sudhakar Yalamanchili
However, these efforts ignored maintaining a balance between bandwidth and compute rate of an architecture, with those of applications, which is a key principle in designing scalable large systems.
Hardware Architecture Performance
no code implementations • 12 Oct 2017 • Duckhwan Kim, Taesik Na, Sudhakar Yalamanchili, Saibal Mukhopadhyay
This paper presents, NeuroTrainer, an intelligent memory module with in-memory accelerators that forms the building block of a scalable architecture for energy efficient training for deep neural networks.
Hardware Architecture
