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Found 41 papers, 10 papers with code
Linearizing Models for Efficient yet Robust Private Inference
Our experimental evaluations show that RLNet can yield models with up to 11. 14x fewer ReLUs, with accuracy close to the all-ReLU models, on clean, naturally perturbed, and gradient-based perturbed images.
When Bio-Inspired Computing meets Deep Learning: Low-Latency, Accurate, & Energy-Efficient Spiking Neural Networks from Artificial Neural Networks
However, advanced ANN-to-SNN conversion approaches demonstrate that for lossless conversion, the number of SNN time steps must equal the number of quantization steps in the ANN activation function.
Recent Advances in Scalable Energy-Efficient and Trustworthy Spiking Neural networks: from Algorithms to Technology
Neuromorphic computing and, in particular, spiking neural networks (SNNs) have become an attractive alternative to deep neural networks for a broad range of signal processing applications, processing static and/or temporal inputs from different sensory modalities, including audio and vision sensors.
Spiking Neural Networks with Dynamic Time Steps for Vision Transformers
Recently proposed SNN training algorithms have significantly reduced the number of time steps (down to 1) for improved latency and energy efficiency, however, they target only convolutional neural networks (CNN).
FixPix: Fixing Bad Pixels using Deep Learning
Efficient and effective on-line detection and correction of bad pixels can improve yield and increase the expected lifetime of image sensors.
Mitigate Replication and Copying in Diffusion Models with Generalized Caption and Dual Fusion Enhancement
While diffusion models demonstrate a remarkable capability for generating high-quality images, their tendency to `replicate' training data raises privacy concerns.
Island-based Random Dynamic Voltage Scaling vs ML-Enhanced Power Side-Channel Attacks
In this paper, we describe and analyze an island-based random dynamic voltage scaling (iRDVS) approach to thwart power side-channel attacks.
Making Models Shallow Again: Jointly Learning to Reduce Non-Linearity and Depth for Latency-Efficient Private Inference
Large number of ReLU and MAC operations of Deep neural networks make them ill-suited for latency and compute-efficient private inference.
Technology-Circuit-Algorithm Tri-Design for Processing-in-Pixel-in-Memory (P2M)
The massive amounts of data generated by camera sensors motivate data processing inside pixel arrays, i. e., at the extreme-edge.
ViTA: A Vision Transformer Inference Accelerator for Edge Applications
Vision Transformer models, such as ViT, Swin Transformer, and Transformer-in-Transformer, have recently gained significant traction in computer vision tasks due to their ability to capture the global relation between features which leads to superior performance.
Learning to Linearize Deep Neural Networks for Secure and Efficient Private Inference
For a similar ReLU budget SENet can yield models with ~2. 32% improved classification accuracy, evaluated on CIFAR-100.
Neuromorphic-P2M: Processing-in-Pixel-in-Memory Paradigm for Neuromorphic Image Sensors
Edge devices equipped with computer vision must deal with vast amounts of sensory data with limited computing resources.
SAL-ViT: Towards Latency Efficient Private Inference on ViT using Selective Attention Search with a Learnable Softmax Approximation
Then, given our observation that external attention (EA) presents lower PI latency than widely-adopted self-attention (SA) at the cost of accuracy, we present a selective attention search (SAS) method to integrate the strength of EA and SA.
Sparse Mixture Once-for-all Adversarial Training for Efficient In-Situ Trade-Off Between Accuracy and Robustness of DNNs
Existing deep neural networks (DNNs) that achieve state-of-the-art (SOTA) performance on both clean and adversarially-perturbed images rely on either activation or weight conditioned convolution operations.
In-Sensor & Neuromorphic Computing are all you need for Energy Efficient Computer Vision
Although the overhead for the first layer MACs with direct encoding is negligible for deep SNNs and the CV processing is efficient using SNNs, the data transfer between the image sensors and the downstream processing costs significant bandwidth and may dominate the total energy.
Hoyer regularizer is all you need for ultra low-latency spiking neural networks
Spiking Neural networks (SNN) have emerged as an attractive spatio-temporal computing paradigm for a wide range of low-power vision tasks.
Towards Energy-Efficient, Low-Latency and Accurate Spiking LSTMs
We obtain test accuracy of 94. 75% with only 2 time steps with direct encoding on the GSC dataset with 4. 1x lower energy than an iso-architecture standard LSTM.
Enabling ISP-less Low-Power Computer Vision
However, direct inference on the raw images degrades the test accuracy due to the difference in covariance of the raw images captured by the image sensors compared to the ISP-processed images used for training.
P2M-DeTrack: Processing-in-Pixel-in-Memory for Energy-efficient and Real-Time Multi-Object Detection and Tracking
The designs also reduce the sensor and total energy (obtained from in-house circuit simulations at Globalfoundries 22nm technology node) per frame by 5. 7x and 1. 14x, respectively.
A Fast and Efficient Conditional Learning for Tunable Trade-Off between Accuracy and Robustness
In this paper, we present a fast learnable once-for-all adversarial training (FLOAT) algorithm, which instead of the existing FiLM-based conditioning, presents a unique weight conditioned learning that requires no additional layer, thereby incurring no significant increase in parameter count, training time, or network latency compared to standard adversarial training.
Toward Efficient Hyperspectral Image Processing inside Camera Pixels
Hyperspectral cameras generate a large amount of data due to the presence of hundreds of spectral bands as opposed to only three channels (red, green, and blue) in traditional cameras.
P2M: A Processing-in-Pixel-in-Memory Paradigm for Resource-Constrained TinyML Applications
Visual data in such cameras are usually captured in the form of analog voltages by a sensor pixel array, and then converted to the digital domain for subsequent AI processing using analog-to-digital converters (ADC).
BMPQ: Bit-Gradient Sensitivity Driven Mixed-Precision Quantization of DNNs from Scratch
Compared to the baseline FP-32 models, BMPQ can yield models that have 15. 4x fewer parameter bits with a negligible drop in accuracy.
Can Deep Neural Networks be Converted to Ultra Low-Latency Spiking Neural Networks?
SOTA training strategies for SNNs involve conversion from a non-spiking deep neural network (DNN).
Pipeline Parallelism for Inference on Heterogeneous Edge Computing
We propose EdgePipe, a distributed framework for edge systems that uses pipeline parallelism to both speed up inference and enable running larger (and more accurate) models that otherwise cannot fit on single edge devices.
HIRE-SNN: Harnessing the Inherent Robustness of Energy-Efficient Deep Spiking Neural Networks by Training with Crafted Input Noise
Low-latency deep spiking neural networks (SNNs) have become a promising alternative to conventional artificial neural networks (ANNs) because of their potential for increased energy efficiency on event-driven neuromorphic hardware.
Training Energy-Efficient Deep Spiking Neural Networks with Single-Spike Hybrid Input Encoding
This paper presents a training framework for low-latency energy-efficient SNNs that uses a hybrid encoding scheme at the input layer in which the analog pixel values of an image are directly applied during the first timestep and a novel variant of spike temporal coding is used during subsequent timesteps.
HYPER-SNN: Towards Energy-efficient Quantized Deep Spiking Neural Networks for Hyperspectral Image Classification
However, the accurate processing of the spectral and spatial correlation between the bands requires the use of energy-expensive 3-D Convolutional Neural Networks (CNNs).
Computational Efficiency
Hyperspectral Image Classification
+1
Towards Low-Latency Energy-Efficient Deep SNNs via Attention-Guided Compression
To evaluate the merits of our approach, we performed experiments with variants of VGG and ResNet, on both CIFAR-10 and CIFAR-100, and VGG16 on Tiny-ImageNet. The SNN models generated through the proposed technique yield SOTA compression ratios of up to 33. 4x with no significant drops in accuracy compared to baseline unpruned counterparts.
A Tunable Robust Pruning Framework Through Dynamic Network Rewiring of DNNs
This paper presents a dynamic network rewiring (DNR) method to generate pruned deep neural network (DNN) models that are robust against adversarial attacks yet maintain high accuracy on clean images.
Formal Verification of Flow Equivalence in Desynchronized Designs
In this work we identify a counterexample to Cortadella et al.'s proof illustrating how their protocol can in fact lead to a violation of flow equivalence.
Logic in Computer Science
Deep-n-Cheap: An Automated Search Framework for Low Complexity Deep Learning
In particular, we show the superiority of a greedy strategy and justify our choice of Bayesian optimization as the primary search methodology over random / grid search.
Pre-defined Sparsity for Low-Complexity Convolutional Neural Networks
We also compared the performance of our proposed architectures with that of ShuffleNet andMobileNetV2.
Neural Network Training with Approximate Logarithmic Computations
The high computational complexity associated with training deep neural networks limits online and real-time training on edge devices.
A Pre-defined Sparse Kernel Based Convolution for Deep CNNs
To explore the potential of this approach, we have experimented with two widely accepted datasets, CIFAR-10 and Tiny ImageNet, in sparse variants of both the ResNet18 and VGG16 architectures.
Pre-Defined Sparse Neural Networks with Hardware Acceleration
Neural networks have proven to be extremely powerful tools for modern artificial intelligence applications, but computational and storage complexity remain limiting factors.
A Highly Parallel FPGA Implementation of Sparse Neural Network Training
We demonstrate an FPGA implementation of a parallel and reconfigurable architecture for sparse neural networks, capable of on-chip training and inference.
Interleaver Design for Deep Neural Networks
We propose a class of interleavers for a novel deep neural network (DNN) architecture that uses algorithmically pre-determined, structured sparsity to significantly lower memory and computational requirements, and speed up training.
Characterizing Sparse Connectivity Patterns in Neural Networks
We propose a novel way of reducing the number of parameters in the storage-hungry fully connected layers of a neural network by using pre-defined sparsity, where the majority of connections are absent prior to starting training.
Accelerating Training of Deep Neural Networks via Sparse Edge Processing
We propose a reconfigurable hardware architecture for deep neural networks (DNNs) capable of online training and inference, which uses algorithmically pre-determined, structured sparsity to significantly lower memory and computational requirements.
