A Low-Cost Neural ODE with Depthwise Separable Convolution for Edge Domain Adaptation on FPGAs

no code implementations • 27 Jul 2021 • Hiroki Kawakami, Hirohisa Watanabe, Keisuke Sugiura, Hiroki Matsutani

It is implemented on Xilinx ZCU104 board and evaluated in terms of domain adaptation accuracy, inference speed, FPGA resource utilization, and speedup rate compared to a software counterpart.

Domain Adaptation Image Classification

Accelerating ODE-Based Neural Networks on Low-Cost FPGAs

no code implementations • 31 Dec 2020 • Hirohisa Watanabe, Hiroki Matsutani

In this paper, using Euler method as an ODE solver, a part of ODENet is implemented as a dedicated logic on a low-cost FPGA (Field-Programmable Gate Array) board, such as PYNQ-Z2 board.

An FPGA-Based On-Device Reinforcement Learning Approach using Online Sequential Learning

no code implementations • 10 May 2020 • Hirohisa Watanabe, Mineto Tsukada, Hiroki Matsutani

In addition, we propose a combination of L2 regularization and spectral normalization for the on-device reinforcement learning so that output values of the neural network can be fit into a certain range and the reinforcement learning becomes stable.

L2 Regularization OpenAI Gym +3