DLA: Compiler and FPGA Overlay for Neural Network Inference Acceleration

no code implementations • 13 Jul 2018 • Mohamed S. Abdelfattah, David Han, Andrew Bitar, Roberto DiCecco, Shane OConnell, Nitika Shanker, Joseph Chu, Ian Prins, Joshua Fender, Andrew C. Ling, Gordon R. Chiu

Overlays have shown significant promise for field-programmable gate-arrays (FPGAs) as they allow for fast development cycles and remove many of the challenges of the traditional FPGA hardware design flow.

Distributed, Parallel, and Cluster Computing Hardware Architecture Signal Processing

An OpenCL(TM) Deep Learning Accelerator on Arria 10

no code implementations • 13 Jan 2017 • Utku Aydonat, Shane O'Connell, Davor Capalija, Andrew C. Ling, Gordon R. Chiu

We show a novel architecture written in OpenCL(TM), which we refer to as a Deep Learning Accelerator (DLA), that maximizes data reuse and minimizes external memory bandwidth.

Image Classification